Field of the Invention
The present invention relates generally to the field of integrated circuit memories. More particularly, the present invention is directed to built-in self test system and method for two-dimensional memory redundancy allocation.
Redundancy is desirable in memories to increase the yield of semiconductor chip production. Semiconductor memories typically comprise very dense circuitry. Due to this high density, memories are relatively susceptible to damage by subtle defects that logic circuits are largely immune from. Thus, yield can be improved by including redundant memory elements, e.g., cells, rows, columns, and I/Os, to replace the corresponding elements containing one or more damaging defects. For example, it is not uncommon for a chip yield to be 25% without redundancy, 50% with row redundancy, and 70% with two-dimensional (row and column) redundancy. Further, it is not uncommon to see very low yields with insufficient redundancy, sometimes below 1%.
Memory chips are typically tested for defects using testing equipment that is external to the chips. Embedded memories, i.e., the one or more memories on board logic and other chips, on the other hand, generally cannot be tested with external equipment. This is so because embedded memories typically do not have any external I/O contacts accessible to external testing equipment. Rather, the I/Os of embedded memories are themselves embedded and communicate directly with the pertinent other circuitry on board the chips, e.g., logic circuitry. It would be impractical, if not impossible, to provide external I/O contacts linked to the embedded I/Os due to the limited amount of space available for wiring the external contacts and internal I/Os to one another for interfacing with testing equipment. Compounding the problem is the fact that many chips containing embedded memory have several memories located at various locations throughout the chips. For these reasons, it is generally most practical to test embedded memories using built-in self test (BIST) circuitry provided on board these chips.
Most SRAMs having redundancy typically have only a single dimension of redundancy implemented using spare rows. When a failure is detected during the test of a given word, the BIST replaces the row containing that word with one of the spare rows. In this manner, all of the words in the defective row are replaced, despite the fact that only one word, or even cell, within that row may have failed. Single-dimensional redundancy works well with a BIST, since it is generally a simple matter to detect a failing word on each word readback from the memory to the BIST circuitry.
FIG. 1 shows a conventional pass/fail comparator 10 for implementing a single-row BIST that includes a simple XOR-OR tree 12 that compares a word 14 (e.g., a 72-bit word) from a row of memory (not shown) with the expected value 18 of that word. This comparison is performed local to memory. Pass/fail comparator 10 generates a pass/fail signal 22 that is sent to the BIST, where the redundancy calculation is stored.
Two-dimensional redundancy has been implemented on DRAMs, SRAMs, and CAMs when required, but is not widely utilized unless absolutely needed due to the relatively high amount of overhead required. FIG. 2 illustrates a conventional circuit 30 for implementing a two-dimensional BIST that includes a plurality of XOR comparators 34 that each compare a bit 36 of word 38 from a row of memory (not shown) with the expected value 42 of that bit. To include column redundancy in its redundancy allocation scheme, circuit 30 further includes a counter 46 for each bit 36 of word 38. A “column” of words is read from row 0 to row n, starting from row 0 and proceeding to row n. Any failing bit(s) 36 in each word 38 are accumulated in counters 46 until the “top” of the memory, i.e., row n, is reached, at which point the data from the counters are read out to the BIST and the counters are reset for testing of the next column of words. The BIST then determines which column(s), if any, of the memory should be replaced by the spare column(s). For example, column 3 may have four failing bits, one in each of four separate words, whereas columns 24 and 61 may each have only 1 failing bit. Accordingly, BIST would determine that column 3 should be replaced with a spare column. Depending upon the availability of spare columns and rows, columns 24 and/or 61 may be replaced with corresponding spare columns or the corresponding row(s) containing the failing bits may be replaced with corresponding spare row(s). If there are more failing rows and columns than spare rows and columns, the memory cannot be repaired. Obviously, the amount of circuit overhead to implement counters 46 (e.g., approximately 4700 cells for a 72-bit word read for the counters and associated clock splitters, etc.), along with the problem of unloading the counters before continuing the BIST testing, creates challenges.